This invention relates generally to the arrangement and size of transistors in semiconductor integrated circuits comprising connected logic cells and more particularly to the construction of a standard logic cell in such circuit comprising insulated gate type transistors.
FIG. 2 illustrates a schematic diagram example of a conventional semiconductor integrated circuit, in this case an OR circuit, composed of standard logic cells of insulated gate type transistors formed by manual cell design per the cell layout shown in FIG. 8. In the OR circuit of FIG. 2, transistors 101, 102, 111 and 112 are input transistors while transistors 105, 115 are output transistors. Transistors 101, 102 and 105 are P-channel insulated gate type transistors (Pch-Tr) and 111, 112 and 115 are N-channel insulation gate type transistors (Nch-Tr).
The circuit of FIG. 2 is has two input terminals 131 and 132 to the gates of Pch-Tr transistors 101, 102 and Nch-Tr transistors 111, 112, wherein Pch-Tr transistors 101, 102 are connected in series at a node 104 to parallel connected transistors 111, 112 across power supply potentials, V.sub.DD and V.sub.SS. Node 104 is connected to the gates of output transistors 105, 115 and output 135 from output transistors 105, 115 is connected to another cell or circuit in the integrated circuit via metal wiring.
FIG. 8 is a layout of the OR circuit shown in FIG. 2 formed through manual design principals wherein the input and output transistors are arranged between power bus, i.e., supply source potential, V.sub.DD, and ground potential, V.sub.SS, and formed in aligned rows or columns relative to aligned diffusion regions. Input transistors 101, 102 and output transistor 105 are P channel devices. Input transistors 111 and 112 and output transistor 115 are N channel devices and are formed in P well 150. Input pair terminals 131, 132 of the cell are connected to respective gate electrodes 120 of Pch-Tr's 101, 102, and Nch-Tr's 111, 112. The drains of output transistors 105, 115 are connected to output terminal 135. Thus, transistors 101-115, polysilicon gate electrodes 120, metal wiring 143 and contacts 145 together comprise the OR circuit shown in FIG. 2.
In order to enhance the operational speed of the logic circuit of the type shown in FIG. 2, it is necessary to widen the channel width, W, of the insulated gate type transistors. For example, the transition period, t.sub.r, in voltage rise of the Pch-Tr's to their ON states can be approximated by the following expression: EQU t.sub.r =4.multidot.C/(.beta..sub.PO .notlessthan.W/n.multidot.V.sub.DD)(1)
where C is the load capacitance; .beta..sub.PO, is the amplification factor in terms of electric current per unit length of the Pch-Tr; W is the channel width; n is the number of the serially connected input transistors; and V.sub.DD is the source potential. Since the transition period, t.sub.r, is inversely proportional to the channel width, W, the transition period, t.sub.r, can be shortened by widening the channel width, W.
In the conventional manual design construction shown in FIG. 8, however, it is necessary to shift transistors 105, 115 up or down in the cell in order to widen channel width, W, of transistors 101, 102, 105, 111, 112 and 115. Concurrently, it is also necessary to modify and rearrange metal wiring 143 and polysilicon gate electrodes 120. Furthermore, it is necessary to move and realign contact 145 of metal wiring 143 and polysilicon 120, as well as other contacts, and realign the contact through holes for the first and second metal layers. This requires additional design work within the set design rules and time checking the necessitated design modifications.
In recent years, there has been developed and adopted a gate array design method to more easily and quickly carry out the necessary modifications in a short period of time. An example of this gate array method is shown in the layout of FIG. 7 for the OR circuit shown in FIG. 2. In this gate array method, transistors of the same size are aligned horizontally relative to each cell so that the correction or changes to transistor channel width can be carried out by widening the channel width of transistors 101, 102, 105, 111, 112 and 115. In the case here, Pch-Tr's 101, 102 and 105 are of the same size and formed along or relative to power bus 141. Nch-Tr's 111, 112 and 115 are of the same size and formed along or relative to ground wiring 142 so that, as illustrated in FIG. 7, a uniformly shaped cell in a substantially aligned array is formed. As a result, the widening of the channel width of these transistors can be carried out in a flexible manner without much design change or correction required to the arrangement of the gate electrodes or the associated metal interconnect wiring.
This adopted gate array method, however, increases the electrical power consumption because the channel width of input transistors 101, 102, 111 and 112 widens as the channel width of output transistors 105 and 115 widens since these transistors are all of the same size. As a result, there is a corresponding increase in penetration current, I.sub.s, which is the current created in charging and discharging of the transistors. For example, the penetrating current, I.sub.s, of the Pch-Tr can be approximated by the following expression: EQU I.sub.s =1/8.multidot..beta..sub.PO .multidot.W/n.multidot.(V.sub.DD -2.multidot.V.sub.th).sup.2 ( 2)
where V.sub.th is the threshold voltage of the transistor and the other symbols in the expression are the same as those set forth in expression (1). As can been seen from expression (2), the penetrating current, I.sub.s, increases as the channel width, W, is increased or becomes wider since the penetrating current, I.sub.s, is proportional to channel width, W.
In particular, the increase in the operational speed of an integrated circuit depends on how much the cell transition time, T.sub.trans, can be shortened. T.sub.trans is the time necessary for a signal to go from an output of a given cell to a next cell to which its output is connected. This time, T.sub.trans, can be calculated on the basis of (1) the relation of the capacitance of the metal wiring connecting the given cell to the next cell, (2) the sum total of the parasitic capacitance, C.sub.L, on the output of the given cell, such as, the capacitance measured by the number of cells connected to the given cell, i.e., the number of fanouts ("FO number"), and (3) expression (1). The capacitance of the metal wiring is correlated to the chip size of an integrated circuit, i.e., the more metal runs utilized in an integrated circuit, which normally increases with increase in chip size, the larger its capacitance. The FO number can be estimated from the chip size. The output transistor channel width, W.sub.o, of the cell is determined by T.sub.trans, calculated by employing the components mentioned above, and the frequency band limits at which the chip is to be used. In the conventional gate array method, the penetrating current of the cells increases significantly because the input transistors are composed of the same channel width as the output transistors, which is proportionate to C.sub.L, with the sum total of the parasitic capacitance on the cell determined as previously mentioned above. As a result, the integrated circuit having a logic cell according to the conventional gate array method requires a significant increase in electric power consumption in order to shorten the switching time of an integrated circuit.
At present, there is an increasing demand for portable electronic apparatus, such as, laptop computers and electronic notebooks that require integrated circuits which operate quickly while consuming little electric power because of the employment of a power source of limited capacity, such as, a battery. However, as previously indicated, it is difficult to realize an integrated circuit employing the cell configuration or structure produced by the conventional gate array method since enhancement of operational speed substantially affects power consumption thereby limiting the usage of battery, powered portable electronic apparatus. Further, it is unrealistic to realize an integrated circuit employing the manual cell design because a significant amount of time is consumed in correction and change of the cell configuration thereby rendering its design cost prohibitive.
It is an object of the present invention to provide a logic cell configuration that permits easy modification of a circuit layout in order to enhance circuit operational speed without significantly sacrificing electrical power consumption.
It is another object of this invention to provide for an improved gate array design method that permits the enhancement of circuit operational speed without significantly increasing electrical power consumption.